Computer Architecture

The function of a computer is to carry out instructions, this occurs within the Central Processing Unit in loop known as a the Fetch-Execute Cycle.

Central Processing Unit

The Central Processing Unit, or CPU is the heart of the computer, it is usually comprised of three main parts:

• The Arithmetic-Logic Unit (or ALU), this is – as the name suggests – where binary arithmetic and logic instructions are carried out. Inside the ALU there are a number of registers – short term memory slots – for storing values during operations, one of these registers is known as the accumulator, but there may be other general purpose registers as well.
• The Control Unit (or CU), this co-ordinates activities taking place in the CPU and between the CPU and peripheral devices via the use of control signals. It is also where instructions are decoded and executed. The CU, like the ALU has a number of registers in it, including:
  • The Program Counter (PC), this holds the address of the next instruction to be executed. Each instruction the processor is going to perform is stored in a memory address; this register is automatically incremented so that it always holds the memory address of the next instruction.
  • The Instruction Register (IR) – sometimes known as a the Current Instruction Register (CIR), This contains the operator and the operand of the current instruction. (Where in the example instruction MOVE 80,#13 “MOVE” is the operator, and “80” and “#13” are the operands.).
  • Status Registers (SR) – this is one register in which each bit of the register represents a different status flag – which is either 1 (flagged) or 0 (not flagged). These are typically used to report information about the result of an operation, for example one flag might represent that an overflow occurred in the operation.
• The System Clock, this sends out timing signals which step the control unit through its operations.

Within the CPU there are also additional registers which deal with accessing memory. The Memory Address Register (MAR) holds the address of a memory location which data will be written to or from, the MAR itself is never written to. Additionally, there is a Memory Data Register (MDR) which holds the data retrieved from or to be written to the address specified in the MAR. The MAR can be written to.

Buses and Lines

A bus is a physical connection which allows data or instructions to be transmitted between different parts of the system. Buses are used to:

• Transfer data between the different points on the CPU
• Transfer data between the CPU and main memory
• Transfer data between computer peripherals and the CPU

In actuality, a bus is a series of lines – a line being a single electrical connection between two points. a line may have a specific name or purpose within a bus, or it may be a general purpose line. Lines are generally one of four types: power, control, data and address. A bus interface bridge is a device which allows communication between different buses.

Operations

The processor obeys instructions in machine code, however since machine code is just a series of binary numbers it is not very human-friendly, instead programming at this level is normally done in an assembly language which uses short mneumonics to represent instructions. The assembly code is then converted to the native machine code by an assembler.

Described below are some primary types of operation a processor can execute. A set of valid operations for a particular processor is known as an instruction set.

Data Transfer

Data transfer operations, or “Load” operations move data from one location to another:

Example commands
MOVE #30, R1 ;Move the number 30 into register 1
LDA R1 ;Load register 1 into the accumulator
STA R2 ;Store the accumulator in register 2

Arithmetic

Data from one location is manipulated, possibly involving data from other locations and the result is stored in a further location.

Example commands
ADC #2 ;Add 2 to the accumulator
SBC #2 ;Subtract 2 from the accumulator
INC ;Increment the accumulator by 1
ABS R1 ;Absolute (positive) value of register 1

Logic

Modern CPU instruction sets have options to perform boolean logic operations on data. Typically this will include the standard operations such as AND, NOT, OR, XOR, NAND and NOR.

Shifts

Shifting operations may alter the location of bits within the number. These shifts tend to be used to examine individual bits within a pattern by moving them into the carry bit position and examining that. Shifts are logical, arithmetic or circular (rotating).

In a logical shift (LSR), bits are moved with no regards as to the previous value of the number, for example after shifting a negative number on bit to the right, a zero is now prefixed to the number, and the number now reads as positive – when in fact it is negative but shifted to the right. The solution to this is an arithmetic shift (ASR), which would in this case prefix a one, to ensure the shifted number is also negative.

In a rotating shift (ROR), the number chomped from the right end of the pattern goes into the carry bit position, and then on the next step of the shift, it is put back at the left end, so that after n number of steps where n is the number of bits in the pattern, the number will be shifted back to its original position.

Branching and Comparing

• Compare (CMP). This can be used to compare two values in the processor; they may be registers, memory locations or fixed values. The result of the comparison will be stored in a status bit ready for use at the next stage of the program.
• Branch If Equal (BEQ) and Branch If Not Equal (BNE) are used to alter the path of executing within a program given the results of a comparison. The operand of this command will be a label or line number to branch (jump) to.
• Jump (JMP) will cause an unconditional jump to a defined label or line in the code given in the operand. The same is true of JSR which will jump to a defined subroutine in the code.

Program to calculate multiplication, with example values of 6x8
MOV #6, X ;Move 6 into register X
MOV #8, Y ;Move 8 into register Y
Loop:
LDA X ;Load X into the accumulator
ADC X ;Add X to the accumulator
STA X ;Store content of accumulator in X
LDA Y ;Load Y into the accumulator
SBC #1 ;Subtract accumulator by 1
STA Y ;Store accumulator in Y
CMP Y, #0 ;Compare Y, our counter, with zero
BNE Loop ;Branch to "Loop" if not equal

Operands and Addressing

When specifying operands there are different sources from which data might be coming, as well as numerous formats that data may take. For example, if we just had an operand of “10”, does this mean 10 in binary, 10 in denary, 10 in hexadecimal, the memory location 10, or something memory location 10 points to? To get around this, we have different addressing modes, and we show these using various special characters, as described below:

LDA #&10	Immediate Addressing. Loads the value “10” in hexadecimal.
LDA #10b	Immediate Addressing. Loads the value “10” in binary
LDA #10	Immediate Addressing. Loads the value “10” in denary
LDA 10	Direct Addressing. Loads the value of memory location number 10
LDA (10)	Indirect Addressing. Loads the memory location which is pointed to by memory location number 10
LDA #5,#100	Base Register Addressing. Loads the memory location formed by adding the first operand to the second (base) operand, so 105. This might be done by means of the index register, X, which is known as Indexed Addressing.
JMP +10	Relative Addressing. Jumps to the instruction located 10 bytes on from the current instruction.

Interrupts

At the end of each Fetch-Execute cycle, the contents of the interrupt registers are checked. Should there be an interrupt; the following steps will typically be taken:

1. The contents of the PC and other registers will be stored safely in a stack.
2. The highest priority interrupt is identified. Interrupts with a lower priority are disabled.
3. The source of the interrupt is identified.
4. The start address of the interrupt handler is loaded into the PC.
5. The interrupt handler is executed.
6. Interrupts are enabled again, and the cycle will restart with any further interrupts.
7. The PC and other registers are “popped” from the stack and restored.8. The user’s program resumes with the next step in its cycle.

Interrupts have different priorities; this is so if two are received simultaneously the computer knows which the more important one to execute first is. Typically there are four levels of priority, which are (in descending order) Hardware Failure, Program Interrupts, Timer Interrupts, I/O Interrupts).

When dealing with an interrupt, the computer has to know which interrupt handler to call for which interrupt. One method of doing this is known as the vectored interrupt mechanism. In this approach a complete list of interrupts and the memory address of their handler is stored in a table called the interrupt vector table. The interrupt supplies an offset number, which identifies the interrupt uniquely. This offset is added to a base term, and the resultant number is the memory address of a pointer to the memory location of the handler routine.

The advantage of this approach is that each interrupt only needs to give the processor an offset number, such as 002, and the processor can determine from that the correct memory location to use. This is more efficient than the interrupt sending the full memory address itself. This approach also allows the interrupt routines to be stored anywhere in the memory, with the pointer table updated to reflect if a handler routine is moved.

Fetch Execute Cycle

The fetch execute cycle is the system driving operations in the CPU, now we have explored the various aspects of a CPU we can see how they interact in the cycle:

Or, in more details we can show the cycle as:

1. CPU sends the address of the next instruction to be executed from the PC to the MAR
2. Increment the PC
3. Get the instruction identified by the MAR into the MDR
4. Move the instruction from the MDR to the IR
5. Move the instruction from the IR to the Control Unit for decoding
   1. Send the operation to the ALU
   2. Put the address of data to be operated upon in a register
6. Send the address for the data from the register to the MAR
7. Read the data from memory into the MDR
8. Move the data from the MDR to an accumulator in the ALU
9. Enact the operation and store the result in an accumulator in the ALU

References:

• Janet Lavery – Durham University Computer Systems, Machine Architecture Lecture 7, 2007
• Janet Lavery – Durham University Computer Systems, Machine Architecture Lecture 8, 2007
• A2 Computing Revision – Paul Nicholls – http://resources.r9paul.org/ASA2/Computing/A2ComputingRevision.pdf
• AS Computing Revision – Paul Nicholls – http://resources.r9paul.org/ASA2/Computing/ASRevisionBook.pdf
  
• A Level Computing – P.M Heathcote